alliance semiconductor 1 h i g h p e r f o r m a n c e 64 k 8 3 . 3 v c m o s s r a m a s 7 c 3 512 l o w v o l t a g e 64 k 8 c m o s s r a m did 11-20015-a. copyright ?1998 alliance semiconductor. all rights reserved. ? logic block diagram a 9 a 8 256 256 8 array (524,288) input buffer a0 a1 a2 a3 a4 a5 a6 a7 a 10 a 11 a 12 a 13 a 14 i/o0 i/o7 vcc gnd oe ce1 we column decoder row decoder control circuit sense amp a 15 ce2 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc a15 ce2 we a13 a8 a9 a11 oe a10 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 nc nc a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd as7c3512 dip, soj selection guide 7c3512-20 7c3512-25 unit maximum address access time 20 25 ns maximum output enable access time 5 6 ns maximum operating current 60 55 ma maximum cmos standby current 2.5 2.5 ma features ? organization: 65,536 words 8 bits ? single 3.3 0.3v power supply ? high speed - 20/25 ns address access time - 5/6 ns output enable access time ? very low power consumption - active: 216 mw max, 20 ns cycle - standby: 9.0 mw max, cmos i/o ? 2.0v data retention ? equal access and cycle times ? easy memory expansion with ce1 , ce2 and oe inputs ? ttl-compatible, three-state i/o ? ideal for cache and portable computing - 75% power reduction during cpu idle mode ? 32-pin jedec standard packages - 300 mil pdip and soj ? esd protection 3 2000 volts ? latch-up current 3 200 ma
as7c3512 2 did 11-20015-a. copyright ?1998 alliance semiconductor. all rights reserved. ? functional description the as7c3512 is a 3.3v high performance cmos 524,288-bit static random access memory (sram) organized as 65,536 words 8 bits. it is designed for memory applications requiring fast data access at low voltage, including pentium ? , powerpc ? , and portable computing. alliances advanced circuit design and process techniques permit 3.3v operation without sacrificing performance or operating ma rgins. the device enters standby mode when ce1 is high or ce2 is low. cmos standby mode consumes 9.0 mw. normal operation offers 75% power reduction after initial access, resulting in significant power savings during cpu idle, suspend, and stretch mode. the as 7c3512 offers 2.0v data retention. equal address access and cycle times (t aa , t rc , t wc ) of 20/25 ns with output enable access times (t oe ) of 5/6 ns are ideal for high performance applications. the active high and low chip enables (ce1 , ce2) permit easy memory expansion with multiple-bank memory systems. a write cycle is accomplished by asserting write enable (we ) and both chip enables (ce1 , ce2). data on the input pins i/o0-i/o7 is written on the rising edge of we (write cycle 1) or the active-to-inactive edge of ce1 or ce2 (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and both chip enables (ce1 , ce2), with write enable (we ) high. the chip drives i/o pins with the data word referenced by the input address. when either chip enable or output enable is inactive, or wr ite enable is active, output drivers stay in high-impedance mode. all chip inputs and outputs are ttl-compatible, and 5v tolerant. operation is from a single 3.30.3v supply. the as7c3512 is pa ckaged in all high volume industry standard packages. absolute maximum ratings stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress ra ting only and functional oper- ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table key: x = dont care, l = low, h = high parameter symbol min max unit power supply voltage relative to gnd v cc C0.5 +4.6 v input voltage relative to gnd v in C0.5 +6.0 v power dissipation p d C1.0w storage temperature (plastic) t stg C55 +150 o c temperature under bias t bias C10 +85 o c dc output current i out C20ma ce1 ce2 we oe data mode h x x x high z standby (i sb , i sb1 ) x l x x high z standby (i sb , i sb1 ) l h h h high z output disable lhhld out read lhlxd in write
as7c3512 3 did 11-20015-a. copyright ?1998 alliance semiconductor. all rights reserved. ? recommended operating conditions (t a = 0c to +70c) ? v il min = C2.0v for pulse width less than t rc /2. dc operating characteristics 1 (v cc = 3.30.3v, gnd = 0v, t a = 0c to +70c) capacitance 2 (f = 1 mhz, t a = room temperature, v cc = 3.3v) parameter symbol min typ max unit supply voltage v cc 3.0 3.3 3.6 v gnd 0.0 0.0 0.0 v input voltage v ih 2.0 - v cc + 0.5 v v il C0.5 ? -0.8v parameter symbol test conditions -20 -25 unit min max min max input leakage current | i li | v cc = max, v in = gnd to v cc C1C1a output leakage current | i lo | ce1 = v ih or ce2 = v il , v cc = max, v out = gnd to v cc C1C1a operating power supply current i cc ce1 = v il , ce2 = v ih , f = f max, i out = 0 ma C 60 C 55 ma standby power supply current i sb ce1 = v ih or ce2 = v il , f = f max C20C20ma i sb1 ce1 3 v cc C0.2v or ce2 0.2v, v in 0.2v or v in 3 v cc C0.2v, f = 0 C2.5C2.5ma output voltage v ol i ol = 8 ma, v cc = min C 0.4 C 0.4 v v oh i oh = C4 ma, v cc = min 2.4 C 2.4 C v parameter symbol signals test conditions max unit input capacitance c in a, ce1 , ce2, we , oe v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
as7c3512 4 did 11-20015-a. copyright ?1998 alliance semiconductor. all rights reserved. ? key to switching waveforms read cycle 3,9,12 (v cc = 3.30.3v, gnd = 0v, t a = 0c to +70c) read waveform 1 3,6,7,9,12 address controlled read waveform 2 3,6,8,9,12 ce1 and ce2 controlled parameter symbol -20 -25 unit notes min max min max read cycle time t rc 20 C 25 C ns address access time t aa C 20 C 25 ns 3 chip enable (ce1 ) access time t ace1 C 20 C 25 ns 3, 12 chip enable (ce2) access time t ace2 C 20 C 25 ns 3, 12 output enable (oe ) access time t oe C5C6 ns output hold from address change t oh 3C3C ns5 chip enable (ce1 ) to output in low z t clz1 3 C 3 C ns 4, 5, 12 chip enable (ce2) to output in low z t clz2 3 C 3 C ns 4, 5, 12 chip disable (ce1 ) to output in high z t chz1 C 5 C 6 ns 4, 5, 12 chip disable (ce2) to output in high z t chz2 C 5 C 6 ns 4, 5, 12 output enable to output in low z t olz 0C0C ns4, 5 output disable to output in high z t ohz C5C6 ns4, 5 chip enable to power up time t pu 0 C 0 C ns 4, 5, 12 chip disable to power down time t pd C 20 C 25 ns 4, 5, 12 undefined output/dont care falling input rising input address d out data valid t oh t aa t rc supply current ce2 oe d out t oe t olz t ace1, t ace2 t chz1, tchz2 t clz1, t clz2 t pu t pd i cc i sb 50% 50% t ohz data valid t rc 1 ce1
as7c3512 5 did 11-20015-a. copyright ?1998 alliance semiconductor. all rights reserved. ? write cycle 11,12 (v cc = 3.30.3v, gnd = 0v, t a = 0c to +70c) write waveform 1 10,11,12 we controlled write waveform 2 10,11,12 ce1 and ce2 controlled parameter symbol -20 -25 unit notes min max min max write cycle time t wc 20 C 25 C ns chip enable (ce1 ) to write end t cw1 12 C 15 C ns 12 chip enable (ce2) to write end t cw2 12 C 15 C ns 12 address setup to write end t aw 12 C 15 C ns address setup time t as 0C0C ns12 write pulse width t wp 12 C 15 C ns address hold from end of write t ah 0C0C ns data valid to write end t dw 10 C 12 C ns data hold time t dh 0C0C ns4, 5 write enable to output in high z t wz C5C5 ns4, 5 output active from write end t ow 3C3C ns4, 5 t aw t ah t wc address we d in d out t dh t ow t dw t wz t wp t as data valid t aw a ddress ce1 we d in d out t cw1, t cw2 t wp t dw t dh t ah t wz t wc t as ce2 data valid
as7c3512 6 did 11-20015-a. copyright ?1998 alliance semiconductor. all rights reserved. ? data retention characteristics data retention waveform ac test conditions notes 1during v cc power-up, a pull-up resistor to v cc on ce1 is required to meet i sb specification. 2 this parameter is sampled and not 100% tested. 3 for test conditions, see ac test conditions , figures a, b, c. 4t clz and t chz are specified with cl = 5pf as in figure c. transition is measured 500mv from steady-state voltage. 5 this parameter is guaranteed but not tested. 6we is high for read cycle. 7ce1 and oe are low and ce2 is high for read cycle. 8 address valid prior to or coincident with ce1 transition low and ce2 transition high. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 ce1 or we must be high or ce2 low during address transitions. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 ce1 and ce2 have identical timing. parameter symbol test conditions min max unit v cc for data retention v dr v cc = 2.0v ce1 3 v cc C0.2v or ce2 0.2v v in 3 v cc C0.2v or v in 0.2v 2.0 C v data retention current i ccdr C 1200 a chip deselect to data retention time t cdr 0Cns operation recovery time t r t rc Cns input leakage current | i li | C1a v cc ce1 t r t cdr data retention mode 3.0v 3.0v v dr 3 2.0v v ih v ih v dr 350 w ? output load: see figure b, except for t clz and t chz see figure c. ? input pulse level: gnd to 3.0v. see figure a. ? input rise and fall times: 5 ns. see figure a. ? input and output timing reference levels: 1.5v. 5 pf* 320 w d out gnd +3.3v 168 w thevenin equivalent: d out +1.72v figure c: output load for t clz , t chz 350 w 30 pf* 320 w d out gnd +3.3v figure b: output load *including scope 10% 90% 10% 90% gnd +3.3v figure a: input waveform and jig capacitance
as7c3512 7 did 11-20015-a. copyright ?1998 alliance semiconductor. all rights reserved. ? typical dc and ac characteristics supply voltage (v) 3.0 3.6 3.3 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb ambient temperature (c) C15 60 85 35 10 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb vs. ambient temperature t a vs. supply voltage v cc i cc i sb i cc i sb ambient temperature (c) -55 80 125 35 -10 0.2 1 0.04 5 25 625 normalized i sb1 (log scale) normalized supply current i sb1 vs. ambient temperature t a v cc = 3.30v supply voltage (v) 3.0 3.6 3.3 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa ambient temperature (c) C15 80 85 35 10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa cycle frequency (mhz) 060 80 40 20 0.0 0.2 0.6 0.8 0.4 1.2 1.2 1.4 normalized i cc normalized supply current i cc vs. ambient temperature t a vs. cycle frequency 1/t rc , 1/t wc vs. supply voltage v cc v cc = 3.3v t a = 25c v cc = 3.3v t a = 25c output voltage (v) 0.0 3.3 1.65 0 10 30 40 20 50 60 70 output source current (ma) output source current i oh output voltage (v) 0.0 3.3 1.65 output sink current (ma) output sink current i ol capacitance (pf) 0750 1000 500 250 0 5 15 20 10 25 30 35 change in t aa (ns) typical access time change d t aa vs. output voltage v ol vs. output capacitive loading vs. output voltage v oh 0 10 30 40 20 50 60 70 v cc = 3.3v t a = 25c v cc = 3.3v t a = 25c v cc = 3.3v
as7c3512 8 did 11-20015-a. copyright ?1998 alliance semiconductor. all rights reserved. ? as7c3512 ordering information as7c3512 part numbering system package \ access time 20 ns 25 ns plastic dip, 300 mil as7c3512-20pc as7c3512-25pc plastic soj, 300 mil as7c3512-20jc AS7C3512-25JC as7c 3 512 Cxx x c sram prefix 3 = 3.3v supply device number access time package:p = pdip 300 mil j = soj 300 mil commercial temperature range, 0c to 70 c
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